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general description the max5195 is an advanced, 14-bit, 260msps digital- to-analog converter (dac) designed to meet the demanding performance requirements of signal synthe- sis applications found in wireless base stations and other communication systems. operating from a single 5v supply, this dac offers exceptional dynamic perfor- mance such as 77dbc spurious-free dynamic range (sfdr) at f out = 19.4mhz, while supporting update rates beyond 260msps. the max5195 current-source array architecture sup- ports a full-scale current range of 10ma to 20ma, which allows a differential output voltage swing between 0.5v p-p and 1v p-p . the max5195 features an integrated 1.2v bandgap ref- erence and control amplifier to ensure high accuracy and low-noise performance. additionally, a separate reference input pin allows the user to apply an external reference source for optimum flexibility. the digital and clock inputs of the max5195 are designed for differential lvpecl-compatible voltage levels. the max5195 is available in a 48-lead qfn package with exposed paddle and is specified for the extended industrial temperature range (-40? to +85?). applications base stations: single-/multi-carrier umts, gsm lmds, mmds, point-to-point microwave direct if synthesis digital-signal synthesis broadband cable systems automated test equipment instrumentation features 260msps output update rate excellent sfdr performance to nyquist (-12dbfs) at 19.4mhz output = 77dbc at 51.6mhz output = 76dbc industry-leading imd performance for 4 tones (-15dbfs) at 18mhz output = 86dbc at 31mhz output = 84dbc low noise performance snr = 160db/hz at f out = 19.4mhz on-chip 1.2v bandgap reference 20ma full-scale current single 5v supply differential lvpecl-compatible digital inputs 48-lead qfn-ep package max5195 14-bit, 260msps high-dynamic performance dac ________________________________________________________________ maxim integrated products 1 ordering information rset av cc av cc av cc av cc agnd agnd av cc refout outp outn ampout d8p d7n d7p clkp clkn d6n d6p d4n d5n d5p d8n d9p 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 dgnd d2n d2p d1p t.p. d0p d0n dv cc d3p d3n d4p dv cc dgnd d10p d10n d11p d11n d12p d12n d13p refin d13n d9n qfn max5195 d1n top view 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 pin configuration 19-2557; rev 0; 7/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX5195EGM -40 c to +85 c 48 qfn-ep* * ep = exposed paddle.
max5195 14-bit, 260msps high-dynamic performance dac 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av cc = dv cc = 5v, agnd = dgnd = 0, external reference v refin = 1.196v, r t = 27.4 ? referenced to av cc , v out = 1v p-p , r set = 3.83k ? , f clk = 156mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc , dv cc to agnd ..............................................-0.3v to +6v av cc , dv cc to dgnd..............................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v d0n d013, d0p d13p, t.p. to dgnd .................-0.3v to +3.6v outp, outn, ampout, refout, clkp, clkn, rset to agnd..........................................-0.3v to +6v refin voltage range...............................................-0.3v to +6v continuous power dissipation (t a = +70 c) 48-pin qfn-ep (thermal resistance ja = +37 c/w)....2162w operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units static performance resolution 14 lsb integral nonlinearity inl best-straight-line fit 2 lsb differential nonlinearity dnl t a = +25 c -3.3 1.5 +3.0 lsb offset error v os (note 1) 0.05 0.1 %fs internal reference 2.5 6 full-scale gain error (note 2) ge external reference 1.6 4 %fs dynamic performance maximum throughput rate f clk 260 mhz signal-to-noise ratio snr full-scale output, within nyquist window, f clk = 260mhz, f out = 19.4mhz 160 db/hz f out = 1mhz, -2dbfs 89 f out = 19.42mhz 77 f clk = 156mhz f out = 51.67mhz 76 f out = 19.4mhz 74 spurious-free dynamic range to nyquist, -12dbfs sfdr f clk = 260mhz f out = 51.61mhz 72 dbc f out = 19.42mhz 82 f clk = 156mhz f out = 51.67mhz 75 f out = 19.42mhz 82 spurious-free dynamic range 10mhz window, -12dbfs sfdr f clk = 260mhz f out = 51.61mhz 76 dbc f out = 1.27mhz -88 f out = 9.53mhz -86 f out = 19.42mhz -82 f out = 28.82mhz -79 f out = 38.42mhz -77 f clk = 156mhz f out = 51.67mhz -79 2nd-order harmonic distortion, -12dbfs hd2 f clk = 260mhz f out = 70.05mhz -72 dbc
max5195 14-bit, 260msps high-dynamic performance dac _______________________________________________________________________________________ 3 electrical characteristics (continued) (av cc = dv cc = 5v, agnd = dgnd = 0, external reference v refin = 1.196v, r t = 27.4 ? referenced to av cc , v out = 1v p-p , r set = 3.83k ? , f clk = 156mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units f out = 1.27mhz -90 f out = 9.53mhz -85 f out = 19.42mhz -81 f out = 28.82mhz -78 f out = 38.42mhz -78 f clk = 156mhz f out = 51.64mhz -79 3rd-order harmonic distortion, -12dbfs hd3 f clk = 260mhz f out = 70.05mhz -80 dbc f out = 18mhz 92 f clk = 156mhz f out = 31mhz 90 f out = 18mhz 91 2-tone imd, -9dbfs, 200khz frequency spacing im3 f clk = 260mhz f out = 31mhz 89 dbc f out = 18mhz 89 f clk = 156mhz f out = 31mhz 87 f out = 18mhz 88 2-tone imd, -12dbfs, 200khz frequency spacing im3 f clk = 260mhz f out = 31mhz 87 dbc f out = 18mhz 86 f clk = 156mhz f out = 31mhz 84 f out = 18mhz 86 4-tone power ratio, -15dbfs, 200khz frequency spacing mtpr f clk = 260mhz f out = 31mhz 84 dbc f out = 18mhz 81 f clk = 156mhz f out = 31mhz 79 f out = 18mhz 81 4-tone power ratio, -18dbfs, 200khz frequency spacing mtpr f clk = 260mhz f out = 31mhz 78 dbc f out = 18mhz 80 f clk = 156mhz f out = 31mhz 77 f out = 18mhz 79 8-tone power ratio, -21dbfs, 200khz frequency spacing mtpr f clk = 260mhz f out = 31mhz 76 dbc f out = 18mhz 75 f clk = 156mhz f out = 31mhz 73 f out = 18mhz 76 8-tone power ratio, -24dbfs, 200khz frequency spacing mtpr f clk = 260mhz f out = 31mhz 74 dbc reference and control amplifier internal reference voltage range v refout 1.136 1.196 1.255 v reference input voltage range v refin 1.196 8% v internal reference voltage drift tco ref 30 v/ c internal reference i sink 200 a sink/source current i source 1.5 ma amplifier input impedance r in 1m ?
note 1: offset error is the deviation of the output voltage from its ideal value at midscale. note 2: full-scale gain error is the deviation of the output voltage from the ideal full-scale value. the actual full-scale voltage is determined by v outp - v outn , when d0p d13p are set high and d0n d13n are set low. note 3: propagation delay is the time difference between the active edge of the clock and the active edge of the output. note 4: power-supply rejection ratio is the full-scale output change as the supply voltage varies over its specified range. max5195 14-bit, 260msps high-dynamic performance dac 4 _______________________________________________________________________________________ electrical characteristics (continued) (av cc = dv cc = 5v, agnd = dgnd = 0, external reference v refin = 1.196v, r t = 27.4 ? referenced to av cc , v out = 1v p-p , r set = 3.83k ? , f clk = 156mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units analog output timing output fall time t fall 90% to 10% 0.8 ns output rise time t rise 10% to 90% 0.8 ns glitch energy 0.5 pv-s timing characteristics data-to-clock setup time (d0n d13n, d0p d13p) t setup referenced to the rising edge, figure 4 0.5 1 ns data-to-clock hold time (d0n d13n, d0p d13p) t hold referenced to the rising edge, figure 4 0.5 1.1 ns propagation delay time t pd (note 3) 0.5 ns minimum clock pulse width high t ch clkp, clkn 1.6 ns minimum clock pulse width low t cl clkp, clkn 1.6 ns logic inputs (d0n?13n, d0p?13p, clkp, clkn) input logic high v ih 2.4 v input logic low v il 1.6 v input logic current, logic high i ih v ih = 2.4v -300 50 +300 a input logic current, logic low i il v il = 1.6v -300 10 +300 a digital input capacitance c in 2pf power supplies analog supply voltage range av cc 4.75 5 5.25 v digital supply voltage range dv cc 4.75 5 5.25 v analog supply current i avcc av cc = dv cc = 5v 48 58 ma digital supply current i dvcc av cc = dv cc = 5v 190 230 ma power dissipation p diss av cc = dv cc = 5v 1190 1440 mw power-supply rejection ratio psrr av cc = dv cc = 5v 5% (note 4) 0.2 %fs/v
max5195 14-bit, 260msps high-dynamic performance dac _______________________________________________________________________________________ 5 integral nonlinearity max5195 toc01 digital input code inl (lsb) 14336 12288 2048 4096 6144 8192 10240 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 16384 differential nonlinearity max5195 toc02 digital input code dnl (lsb) 14336 12288 10240 8192 6144 4096 2048 -2 -1 0 1 2 3 -3 0 16384 reference voltage vs. temperature max5195 toc03 temperature ( c) v refout (v) 60 35 10 -15 1.17 1.18 1.19 1.20 1.16 -40 85 reference voltage vs. analog supply voltage max5195 toc04 analog supply voltage (v) v refout (v) 5.125 5.000 4.875 1.1888 1.1892 1.1896 1.1900 1.1904 1.1884 4.750 5.250 offset error vs. temperature max5195 toc05 temperature ( c) offset error (%fs) 60 35 10 -15 -0.08 -0.06 -0.04 -0.02 0 -0.10 -40 85 gain error vs. temperature max5195 toc06 temperature ( c) gain error (%fs) 60 35 10 -15 1.55 1.60 1.65 1.70 1.75 1.50 -40 85 supply current vs. temperature max5195 toc07 temperature ( c) i avcc , i dvcc (ma) 60 35 10 -15 50 100 150 200 250 0 -40 85 digital supply current analog supply current supply current vs. supply voltage max5195 toc08 analog supply voltage (v) i avcc , i dvcc (ma) 5.125 5.000 4.875 50 100 150 200 250 0 4.750 5.250 digital supply current analog supply current spurious-free dynamic range vs. output frequency (f clk = 156.072mhz) max5195 toc09 f out (mhz) sfdr (dbc) 70 60 50 40 30 20 10 50 60 70 80 90 100 40 080 -6dbfs -12dbfs -18dbfs typical operating characteristics (av cc = dv cc = 5v, external reference v refin = 1.196v, f clk = 156.072mhz, r t = 27.4 ? referenced to av cc , c l = 15pf, v out = 1v p-p , r set = 3.83k ? , t a = +25 c, unless otherwise noted.)
max5195 14-bit, 260msps high-dynamic performance dac 6 _______________________________________________________________________________________ spurious-free dynamic range vs. output frequency (f clk = 208.096mhz) max5195 toc10 f out (mhz) sfdr (dbc) 100 80 60 40 20 50 60 70 80 90 100 40 0 120 -6dbfs -12dbfs -18dbfs spurious-free dynamic range vs. output frequency (f clk = 260.12mhz) max5195 toc11 f out (mhz) sfdr (dbc) 120 100 80 60 40 20 50 60 70 80 90 100 40 0 140 -6dbfs -12dbfs -18dbfs spurious-free dynamic range vs. output frequency (f clk = 312.144mhz) max5195 toc12 f out (mhz) sfdr (dbc) 120 100 80 60 40 20 50 60 70 80 90 100 40 0 160 140 -6dbfs -12dbfs -18dbfs spurious-free dynamic range vs. temperature (f out = 16mhz at -12dbfs) max5195 toc13 temperature ( c) sfdr (dbc) 60 35 10 -15 78 79 80 81 82 83 77 -40 85 f clk = 160mhz spectral plot, single-tone sfdr for a 10mhz window max5195 toc14 output frequency (mhz) amplitude (dbm) 28 26 22 24 14 16 18 20 12 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 10 f center f clk = 156.072mhz f center = 19.416 mhz output amplitude: -12dbfs spectral plot, single-tone sfdr for a 10mhz window max5195 toc15 output frequency (mhz) amplitude (dbm) 28 26 22 24 14 16 18 20 12 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 10 f center f clk = 260.12mhz f center = 19.3975mhz output amplitude: -12dbfs spurious-free dynamic range vs. clock frequency (f out = 19mhz) max5195 toc16 f clk (mhz) sfdr (dbc) 300 270 240 210 180 69 73 77 81 85 65 150 330 -6dbfs -12dbfs -18dbfs multitone (4 tones) power ratio vs. clock frequency max5195 toc17 f clk (mhz) 4-tone mtpr (dbc) 300 270 240 210 180 -90 -85 -80 -75 -70 -95 150 330 32mhz/-18dbfs 18mhz/-18dbfs 32mhz/-15dbfs 18mhz/-15dbfs typical operating characteristics (continued) (av cc = dv cc = 5v, external reference v refin = 1.196v, f clk = 156.072mhz, r t = 27.4 ? referenced to av cc , c l = 15pf, v out = 1v p-p , r set = 3.83k ? , t a = +25 c, unless otherwise noted.)
max5195 14-bit, 260msps high-dynamic performance dac _______________________________________________________________________________________ 7 multitone (8 tones) power ratio vs. clock frequency max5195 toc18 f clk (mhz) 8-tone mtpr (dbc) 300 270 240 210 180 -82.0 -79.0 -76.0 -73.0 -70.0 -85.0 150 330 32mhz/-24dbfs 18mhz/-24dbfs 32mhz/-21dbfs 18mhz/-21dbfs output rise/fall times max5195 toc19 1ns/div 200mv/div 10% 90% pin description typical operating characteristics (continued) (av cc = dv cc = 5v, external reference v refin = 1.196v, f clk = 156.072mhz, r t = 27.4 ? referenced to av cc , c l = 15pf, v out = 1v p-p , r set = 3.83k ? , t a = +25 c, unless otherwise noted.) pin name function 1 d9p data bit 9 2 d8n complementary data bit 8 3 d8p data bit 8 4 d7n complementary data bit 7 5 d7p data bit 7 6 clkp converter clock input. positive input terminal for lvpecl-compatible differential converter clock. 7 clkn complementary converter clock input. negative input terminal for lvpecl-compatible differential converter clock. 8 d6n complementary data bit 6 9 d6p data bit 6 10 d5n complementary data bit 5 11 d5p data bit 5 12 d4n complementary data bit 4 13 d4p data bit 4 14 d3n complementary data bit 3 15 d3p data bit 3 16, 47 dv cc digital supply voltage. accepts a 4.75v to 5.25v supply voltage range. bypass to dgnd with a capacitor combination of 10f in parallel with 0.1f and 47pf. 17, 46 dgnd digital ground 18 d2n complementary data bit 2 19 d2p data bit 2 20 d1n complementary data bit 1 21 d1p data bit 1 22 d0n complementary data bit 0 (lsb)
max5195 14-bit, 260msps high-dynamic performance dac 8 _______________________________________________________________________________________ pin description (continued) pin name function 23 d0p data bit 0 (lsb) 24 t.p. test point. must be connected to lvpecl high level (2.4v) for optimum dynamic performance. 25, 29, 32, 33, 35 av cc analog supply voltage. accepts a 4.75v to 5.25v supply voltage range. bypass to agnd with a capacitor combination of 10f in parallel with 0.1f and 47pf. 26 refout reference output. output of the internal 1.2v precision bandgap reference. bypass with a 1f capacitor to agnd, if an external reference source is used. 27, 28 agnd analog ground 30 outn complementary dac output. negative terminal for differential voltage output. 31 outp dac output. positive terminal for differential voltage output. 34 ampout control amplifier output. for stable operation, bypass to agnd with a combination of a 3k ? resistor in parallel with a 1.5f tantalum capacitor. 36 rset output current set resistor. external resistor (3.83k ? to 7.66k ? ) sets the full-scale current of the dac. 37 refin reference input. accepts an input voltage range of 1.196v 8%. bypass to agnd with a 0.1f capacitor, when used with the internal bandgap reference. 38 d13n complementary data bit 13 (msb) 39 d13p data bit 13 (msb) 40 d12n complementary data bit 12 41 d12p data bit 12 42 d11n complementary data bit 11 43 d11p data bit 11 44 d10n complementary data bit 10 45 d10p data bit 10 48 d9n complementary data bit 9
detailed description architecture the max5195 is a high-performance, 14-bit, segmented current-source array dac (figure 1) capable of operat- ing with clock speeds up to 260mhz. the converter consists of separate input and dac registers, followed by a current-source array. this current-source array is capable of generating differential full-scale currents in the range of 10ma to 20ma. an internal r2r resistor network, in combination with external 27.4 ? termination resistors, convert these differential output currents into a differential output voltage with a peak-to-peak output voltage range of 0.5v to 1v. an integrated 1.2v bandgap reference, control amplifier, and user-selec- table, external resistor determine the data converter s full-scale output range. internal reference and control amplifier the max5195 supports operation with the on-chip 1.2v bandgap reference or an external reference voltage source. refin serves as the input for an external refer- ence source, and refout provides a 1.2v output volt- age, if the internal reference is used. for internal reference operation, refin and refout must be con- nected together and decoupled to agnd with a 1f capacitor in parallel with a 0.1f capacitor for stable operation. the max5195 reference circuit also employs a control amplifier, designed to regulate the full-scale current i fs for the differential current outputs of the max5195. for stable operation, the output ampout of this amplifier must be bypassed with a 3k ? resistor in parallel with a 1.5f tantalum capacitor to agnd. configured as a voltage-to-current amplifier, the output current can be calculated as follows: i fs = 64 ? i ref - 1lsb max5195 14-bit, 260msps high-dynamic performance dac _______________________________________________________________________________________ 9 av cc outp outn agnd 1.2v reference current-source array input latch input register clkp clkn r2r network refout refin rset dv cc dgnd d0n/d0p?13n/d13p 14 decoder bias max5195 figure 1. simplified max5195 block diagram
max5195 i fs = 64 ? i ref - (i fs / 2 14 ) where i ref is the reference output current (i ref = v refout /r set ) and i fs is the full-scale current. r set is the reference resistor that determines the amplifier s output current (figure 2) on the max5195. see table 1 for a matrix of different i fs and r set selections. external reference operation figure 3 illustrates a low-impedance reference source applied to the data converter for external reference operation. refin allows an input voltage range of 1.196v 8%. use a fixed output voltage reference source such as the 1.2v, 25ppm/ c (typ) max6520 bandgap reference for improved accuracy and drift performance. bypass the unused refout pin of the max5195 with a 1f capacitor to agnd. 14-bit, 260msps high-dynamic performance dac 10 ______________________________________________________________________________________ outp outn 1.2v reference current-source array refout refin rset note: connect refin and refout together for internal reference operation. av cc i ref 0.1 f1 f 1.5 f 3k ? i ref = v refout /r set max5195 outp outn 1.2v reference current-source array refout refin rset av cc i ref 1 f 1.5 f 3k ? i ref = v refout /r set ampout max6520 max5195 figure 3. external reference configuration using the max6520 r set (k ? ) full-scale current i fs (ma) reference current i ref (a) calculated 1% eia std output voltage v outp/n * (mv p-p ) 10 156.26 7.68 7.50 500 12 187.50 6.40 6.34 600 14 218.80 5.49 5.49 700 16 250.00 4.80 4.75 800 18 281.30 4.27 4.22 900 20 312.50 3.84 3.83 1000 table 1. i fs and r set selection matrix based on a typical 1.2v reference voltage * terminated into a 27.4 ? load (see analog outputs section for details) referenced to av cc . figure 2. internal reference configuration
lvpecl-compatible digital inputs (d0p?13p, d0n?13n) the max5195 digital interface consists of 14 differen- tial, lvpecl-compatible digital input pins. these inputs follow standard positive binary coding where d0p and d0n represent the differential inputs to the least signifi- cant bit (lsb), and d13p and d13n represent the dif- ferential pair associated with the most significant bit (msb). d0p/n through d13p/n accept lvpecl input levels of 0.8v p-p (table 2). each of the digital input terminals can be terminated with a separate 50 ? resistor; however, to achieve the lowest noise performance, it is recommended to termi- nate each differential pair with a 100 ? resistor located between the positive and negative input terminals. clock inputs (clkp, clkn) and data timing relationship the max5195 features differential, lvpecl-compatible clock inputs. internal edge-triggered flip-flops latch the input word on the rising edge of the clock-input pair clkp/clkn. the dac is updated with the data word on the next rising edge of the clock input. this results in a conversion latency of one clock cycle. the max5195 provides for minimum setup and hold times (<2ns), allow- ing for noncritical external interface timing (figure 4). for best ac performance, a differential, dc-coupled clock signal with lvpecl-compatible voltage levels (table 2) should be used. the max5195 operates properly with a clock duty cycle set within the limits list- ed in the electrical characteristics table. however, a 50% duty cycle should be utilized for optimum dynamic performance. to maintain the dac s excellent dynamic performance, clock and data signals should originate from separate signal sources. analog outputs (outp, outn) the max5195 s current array is designed to drive full- scale currents of 10ma to 20ma into an internal r2r resistor network (r r2r ). to achieve the desired differ- ential output voltage range of 0.5v p-p to 1v p-p , both outp and outn should be externally terminated into 27.4 ? (r t ), resulting in a combined load of r load = 25 ? (figure 5): r load = r r2r || r t r load = (285 ? ? 27.4 ? ) / (285 ? + 27.4 ? ) r load = 25 ? max5195 14-bit, 260msps high-dynamic performance dac ______________________________________________________________________________________ 11 parameter minimum lvpecl specification maximum lvpecl specification input voltage high v cc ** - 1.16v v cc ** - 0.88v input voltage low v cc ** - 1.81v v cc ** - 1.48v common-mode level v cc ** - 1.3v table 2. lvpecl voltage levels ** v cc is the supply voltage associated with the lvpecl source. a typical v cc level associated with lvpecl is 3.3v, which sets the common-mode level to 2v, allowing a typical peak-to-peak signal swing of 0.8v. clkp clkn d13 d0 outp outn 10% point 90% point t ch t setup t hold t pd t cl t rise , t fall max5195 figure 4. input/output timing information
max5195 with a full-scale current of 10ma (20ma), both outputs outp and outn achieve a 0.25v (0.5v) voltage swing each, resulting in a 0.5v p-p (1v p-p ) differential output signal. for applications that require an even smaller output voltage swing, the termination resistor value r t can be as low as 0 ? . the proportional, differential output voltages can then be used to drive a wideband rf transformer or a fast, low-noise, low-distortion operational amplifier to convert the differential voltage into a single-ended output. the max5195 analog outputs can also be configured in single-ended mode. for more details on different output configurations, see the applications information section. applications information differential coupling using a wideband rf transformer a wideband rf transformer such as the ttwb1010 (1:1 turns ratio) from coilcraft can be used to convert the max5195 differential output signal to a single-ended signal (figure 6). as long as the generated output spectrum is within the passband of the transformer, a differentially coupled transformer provides the best dis- tortion performance. additionally, the transformer helps to reject noise and even-order harmonics, provides electrical isolation, and is capable of delivering more power to the load. single-ended unbuffered output configuration figure 7a shows an unbuffered single-ended output, which is suitable for applications requiring a unipolar voltage output. the nominal termination resistor load of 27.4 ? (referred to av cc ) results in a differential output 14-bit, 260msps high-dynamic performance dac 12 ______________________________________________________________________________________ max5195 av cc agnd ampout r r2r 285 ? r r2r 285 ? av cc av cc r t 27.4 ? r t 27.4 ? outp outn r load = 25 ? r load = 25 ? r load is the combined load of the internal r2r resistor network in parallel with the external termination resistor. figure 5. simplified output architecture d0 d13 14 av cc , dv cc agnd, dgnd av cc av cc outp outn r t 27.4 ? r t 27.4 ? 1 : 1 ttwb1010 v out , single ended agnd agnd wideband rf transformer performs differential-to- single-ended conversion. max5195 figure 6. differential coupling using a wideband rf transformer
swing of 1v p-p (0.5v p-p single ended) when applying a full-scale current of 20ma. alternatively, an external unity-gain amplifier can be used to buffer the outputs. this circuit works as an i-v amplifier (figure 7b), in which outp is held at av cc by the inverting terminal of the buffer amplifier. outn should then be connected to av cc to provide a dc- current path for the current switched to outp. the amplifier s maximum output swing and the max5195 full-scale current determine the value of r loop . an optional roll-off capacitor (c loop ) in the feedback loop helps to ease dv/dt requirements at the input of the operational amplifier. it is recommended that the ampli- fier s power-supply rails be higher than the resistor s output reference voltage av cc due to its positive and negative output swing around av cc . max5195 14-bit, 260msps high-dynamic performance dac ______________________________________________________________________________________ 13 d0 d13 av cc , dv cc agnd, dgnd av cc av cc outp outn r t 27.4 ? r t 27.4 ? agnd agnd max5195 14 v outp v outn v out_ = i fs r load r load : resistor combination of internal r2r network and external termination resistor figure 7a. single-ended unbuffered output configuration d0 d13 av cc , dv cc agnd, dgnd av cc outp outn agnd max5195 14 v out r loop c loop figure 7b. single-ended buffered output configuration
max5195 grounding, bypassing, and power-supply considerations grounding and power-supply decoupling can strongly influence the performance of the max5195. unwanted digital crosstalk can couple through the input, refer- ence, power supply, and ground connections, thus affecting dynamic performance. proper grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. this reduces emi and internal crosstalk, which can also affect the dynamic performance of the max5195. use of a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes is recommend- ed. high-speed signals should be run on lines directly above the ground plane. since the max5195 has sepa- rate analog and digital ground buses (agnd and dgnd, respectively), the pc board should have sepa- rate analog and digital ground sections with only one point connecting the two planes. digital signals should run above the digital ground plane and analog signals above the analog ground plane. digital signals should be kept as far away from sensitive analog inputs, refer- ence input lines, and clock inputs. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. the max5195 has two separate power-supply inputs for analog (av cc ) and digital (dv cc ). each av cc input should be decoupled with parallel ceramic chip capac- itors of 10f in parallel with 0.1f and 47pf with these capacitors as close to the supply pins as possible and their opposite ends with the shortest possible connec- tion to the ground plane (figure 8). the dv cc pins should also have separate 10f in parallel with 0.1f and 47pf capacitors adjacent to their respective pins. try to minimize the analog and digital load capaci- tances for proper operation. 14-bit, 260msps high-dynamic performance dac 14 ______________________________________________________________________________________ agnd 1.2v reference current-source array input latch input register clkp clkn r2r network refout refin rset d0n/d0p d13n/d13p 14 decoder bias dv cc dgnd 5v outp outn agnd agnd agnd 0.1 f 1 f 3.83k ? 3k ? 27.4 ? 27.4 ? 260mhz, lvpecl 2v 1.6v 2.4v 1.5 f ampout av cc 10 f 0.1 f 47pf 47pf 0.1 f 10 f 5v v out max5195 figure 8. decoupling and bypassing techniques for max5195?ypical operating circuit
the power-supply voltages should also be decoupled at the point where they enter the pc board with tanta- lum or electrolytic capacitors. ferrite beads with addi- tional decoupling capacitors forming a network can also improve performance. the analog and digital power-supply inputs av cc and dv cc of the max5195 allow a 4.75v to 5.25v supply voltage range. enhanced thermal dissipation qfn-ep package the max5195 is packaged in a thermally enhanced 48- pin qfn-ep package, providing greater design flexibili- ty, increased thermal efficiency, and a low thermal junction-case ( jc) resistance of 2 c/w. in this pack- age, the data converter die is attached to an ep lead frame. the back of the lead frame is exposed at the package bottom surface (the pc board side of the package, figure 9. this allows the package to be attached to the pc board with standard infrared (ir) flow soldering techniques. a specially created land pat- tern on the pc board, matching the size of the ep (5.5mm ? 5.5mm), guarantees proper attachment of the chip, and can also be used for heat-sinking purposes. designing thermal vias* into the land area and imple- menting large ground planes in the pc board design further enhance the thermal conductivity between board and package. to remove heat from a 48-pin qfn-ep package effectively, an array of 3 ? 3 (or greater) vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) is recommended. a smaller via array can be used as well, but results in an increased ja. note that efficient thermal management for the max5195 is strongly dependent on pc board and circuit design, component placement, and installation; therefore, exact performance figures cannot be provided. for more infor- mation on proper design techniques and recommenda- tions to enhance the thermal performance of parts such as the max5195, refer to amkor technology s website at www.amkor.com. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nulli- fied. for a dac, the deviations are measured every individual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step height and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. max5195 14-bit, 260msps high-dynamic performance dac ______________________________________________________________________________________ 15 die copper trace, 1oz top layer ground plane (agnd) ground plane agnd, dgnd power plane 3 x 3 array of thermal vias thermal land copper plane, 1oz exposed pad epoxy bonding wire 48-lead qfn package with exposed pad copper trace, 1oz pc board max5195 figure 9. max5195 exposed paddle/pc board cross section * connect the land pattern to internal or external copper planes.
max5195 offset error the offset error is the difference between the ideal and the actual offset point. for a dac, the offset point is the step value when the digital input is at midscale. this error affects all codes by the same amount. gain error a gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. glitch energy glitch impulses are caused by asymmetrical switching times in the dac architecture, which generates unde- sired output transients. the amount of energy that appears at dac s output is measured over time and is usually specified in the pv-s range. dynamic performance parameter definitions signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog output (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum can be derived from the dac s resolution (n bits): snr db = 6.02 db ? n + 1.76 db however, noise sources such as thermal noise, refer- ence noise, clock jitter, etc., affect the ideal reading. snr is therefore computed by taking the ratio of the rms signal to the rms noise, which includes all spec- tral components minus the fundamental, the first four harmonics, and the dc offset. spurious-free dynamic range sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal components) to the rms value of the next largest distortion component. sfdr is measured in dbc, with respect to the carrier frequency amplitude. multitone power ratio (mtpr) a series of equally spaced ones is applied to the dac with one tone removed from the center of the range. mtpr is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequen- cies), which appears as the largest spur at the frequency of the missing tone in the sequence. this test can be performed with any number of input tones; however, four and eight tones are among the most common test condi- tions for cdma- and gsm/edge-type applications. intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc of either input tone to the worst 3rd-order (or higher) imd prod- ucts. note that 2nd-order imd products usually fall at frequencies, which can be easily removed by digital fil- tering. therefore, they are not as critical as 3rd-order imds. the two-tone imd performance of the max5195 was tested with the two individual input tone levels set to -9dbfs and -12dbfs. chip information transistor count: 15,000 process: sige 14-bit, 260msps high-dynamic performance dac 16 ______________________________________________________________________________________
max5195 14-bit, 260msps high-dynamic performance dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn 28, 32,44, 48l.eps

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